Experience:
Not specified
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Employment Type:
Full time
Posted:
3/18/2018
Job Category:
Other
Engineeers
(This job is no longer available)
Xilinx | San Jose, CA
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Job Description

Engineers Xilinx, Inc. in San Jose, CA seeks: Senior Design Engineer (Embedded Software) (154886). Oversee definition, design, verification, & documentation for Xilinx ASIC development & embedded sys & processors. Reqs incl MS or foreign equiv in Elect Eng, Comp Sci, Comp Eng or rel + 2 yrs prog rel exp. Alt reqs incl BS or foreign equiv + 5 yrs prog rel exp. Senior Process Development Engineer (154939). Understand power, performance & area targets for current Xilinx FPGA family. Reqs incl MS or foreign equiv in Elect Eng or rel + 2 yrs rel exp. Senior Design Engineer (154940). Oversee verif & doc for app-specific integrated circuit (ASIC) & FPGA chip dvlpmt. Reqs incl MS or foreign equiv in Elect Eng, Comp Eng, Comp Sci or rel + 4 yrs prog rel exp. Alt reqs incl BS or foreign equiv + 6 yrs prog rel exp. Sr. Staff Design Engineer (FPGA Package Dvpmt) (154945). Oversee def, design, verif, & doc for Xilinx FPGA dvlpmt & package design architecture & matrix def. Reqs incl BS or foreign equiv in Elect Eng or rel + 7 yrs prog rel exp. Senior Staff Product Applications Engineer (154947). Utilize domain knowledge, design expertise & access to state of the art silicon & dvlpmt tools. Reqs incl BS or foreign equiv in Comp Sci, Comp Eng, Elect Eng or rel + 7 yrs prog rel exp. Alt reqs incl MS or foreign equiv + 5 yrs prog rel exp. Design Engineer (Design and Verification) (154956). Oversee def, des, verif, and doc ASIC devpmt. Specifically Ethernet MAC and Interlaken blocks. Reqs incl. MS or fgn equiv in CS, EE, or rel. Staff Design Engineer (154951). Oversee def, design, verif, and doc for Xilinx ASIC dvpmt. Reqs incl. BS or fgn equiv in Elect or Electronic Engg, or rel + 6 yrs prog rel exp. Will accept MS or fgn equiv + 4 yrs rel exp. Staff Design Engineer (Verification) (154953). Design, dev, or test electronic components for ASIC devpmt. Reqs incl. MS or fgn equiv in Elect Engg, CE, CS, or rel + 4 yrs rel exp. Will accept BS or fgn equiv + 6 yrs prog rel exp. Senior Design Verification Engineer (154955). Oversee def, design, verif, and doc for ASIC devpmt. Reqs incl. BS or fgn equiv in Elect or Electronic Engg, Instrument Engg, CS, CE, or rel + 5 yrs prog rel exp. Will accept MS or fgn equiv + 3 yrs rel exp. Staff Product Applications Engineer (154954). Drive the creation and adoption of new software features for applications used in the Xilinx FPGA design flow. Reqs incl. BS or fgn equiv in CE, Elect Engg, or rel +5 yrs prog rel exp. Apply to job code at http://careers.xilinx.com. EEO/AA/Vet/Disability Employer
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