Experience:
No experience
Employment Type:
Full time
Posted:
12/5/2017
Job Category:
Engineering
New Grad - ASIC / FPGA Design Engineer
(This job is no longer available)
ViaSat | Cleveland, OH
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Job Description

Requirements

* Bachelor's or Master's Degree in Electrical Engineering
* Educational focus on Digital Design and Design Verification
* Demonstrated ability to design and implement using Verilog or System Verilog language
* Demonstrated ability to verify digital logic designs with System Verilog and Universal Verification Methodology (UVM)
* Excellent written and verbal communication skills
* Ability to travel up to 10%