Experience:
0-1 years of experience
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Employment Type:
Full time
Posted:
10/28/2016
Job Category:
Engineering
Associate Rotation Engineer - DFT - 5312
(This job is no longer available)
State of Oregon | Wilsonville, OR
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Job Description

- - - # Associate Rotation Engineer - DFT - 5312 - - - # Description ## Company: Mentor Graphics Job Title: Associate Rotation Engineer - DFT - 5312 Job Location: US - OR - Wilsonville Job Category: College All qualified applicants will receive consideration for employment without regard to race, sex, sexual orientation, gender expression or identity, color, religion, national origin, disability or protected veteran status. **Job Duties:** Overview: In this position, you will be involved in a structured Associate Rotation Engineer Training Program. This is a fast-track training program that challenges you to develop the expertise needed to solve difficult technical problems. Associate Rotational Engineers are members of a team of highly motivated individuals working with customers designing the most complex hardware and software systems in the world and whose applications span the electronics industry. This training program will give you unique insight into our technical marketing and product support divisions as well as our sales organization. Upon successful completion of the training program, you will be eligible to advance into one of these organizations. Post program opportunities include Field Application Engineer, Corporate Applications Engineer and Technical Marketing Engineer positions. **Start date for this position is Summer, 2017** **Job Qualifications:** New graduate (2017) BSEE/MSEE (Master's degree is preferred). Familiar with VLSI design, HDL Synthesis, VLSI testing and design for testability. Experience with design, simulation, verification of ASIC/VLSI circuits and systems, design verification and product test generation preferred. In-depth understanding of Design for Test (DFT) structures is required. This includes scan based testing, Memory BIST, Logic BIST, and Boundary Scan (1149.1). Knowledge of scan data compression methodologies desired. Preferred experience in specific areas: Operating Systems: UNIX, Linux, Sun Solaris. Languages: Verilog (Behavioral, RTL, gate level), VHDL (Behavioral, RTL, gate level), Perl, C/C++. CAD. Tools: Synthesis, Simulation, ATPG, Memory BIST, Logic BIST, Boundary Scan. Familiarity with FastScan, FlexTest, LBISTArchitect, MBISTArchitect, and BSDArchitect a plus. Strong trouble shooting skills and ability to break a complex problem into its components. Excellent verbal and written communication skills; very self-motivated and results-oriented. Travel may be required. Ability to relocate if needed. This position may require access to export-controlled technology. If an export license is required and Mentor Graphics elects to apply for such a license, then candidates must be approved and licensed by the applicable government authorities as a condition of employment.