Experience:
No experience
Employment Type:
Full time
Posted:
8/4/2019
Job Category:
Engineering
Intern_Signal Integrity / Power Integrity Engineer
(This job is no longer available)
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Job Description

Job Description:

* Responsible for high-speed SSD board designs, pre layout simulation, post layout simulation and design layout guidelines generation for DDR4, LPDDR4, PCIe Gen3/4, ONFI and PDN.
* Provide SI/PI expertise for SSD controller package substrate design and SSD PCB design.
* Work closely with SoC, FW, Package, and Circuit design engineers locally and remotely.

Qualifications:

* BSEE or MSEE
* Strong understanding of electromagnetics, specifically electromagnetic waves including transmission line theory and PCB layout or package design techniques
* Experience of EM field solvers, time and frequency domain simulation tools like Sigrity, Allegro, ADS, HFSS, SIWAVE, HSPICE, etc..
* Understanding of high volume manufacturing environments
* Familiar with DDR operation and PCIe operation which need optimization between driver and receiver equalization schemes
* Simulation - Measurement correlation by using Oscilloscope, VNA and TDR experience
* Optimizing PDN including power budget calculation
* ADS or Ansys based DDR all channel time domain simulation
* Extracting PDN for PSIJ Analysis
* PSIJ Analyses including DDR channel and PDN extracted model
* Self-motivated and should enjoy work