Experience:
Not specified
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Employment Type:
Full time
Posted:
2/13/2018
Job Category:
Engineering
Physical Design Eng
(This job is no longer available)
Intel | Santa Clara, CA
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Job Description

Physical Design Eng—Create bottom-up elements of chip design, including FET, cell, and block-level custom layouts, FUB-level floor plans, abstract view generation, RC extraction, and schematic-to-layout verification and debug. Requires MS (#3481); or MS+1 yr exp (#3482). 


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