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Entry-Level Digital ASIC Design Engineer
HP, Inc. | Boise, Idaho
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Job Description

Job Summary:

In this highly visible and challenging role, you will be part of a high performing SOC design and integration team responsible for delivering ASICs that enable world-class Print, Scan, and Copy products and solutions to millions of customers. You will be interfacing with all disciplines (FW, board, Imaging, etc.), with a critical impact on the success of the HP Print business..


As an ASIC Design Engineer, you will have responsibilities spanning various aspects of SOC design:

* Write microarchitecture and/or design specifications
* Design, implement, and debug complex logic designs on a block-level and full-chip level
* Integrate complex IPs and subsystems into the SOC
* Support all front-end integration activities like Lint, CDC, Synthesis, LEC, STA, and ECO
* FPGA prototyping and emulation
* Interface with firmware and systems teams to ensure a high quality end products

Education and Experience Required:

* Bachelor's or Master's degree in Electrical Engineering or Electrical and Computer Engineering
* New college graduate

Knowledge and Skills:

* Proficient with Verilog and SystemVerilog HDL and design methodology
* Hands on experience with digital simulation, synthesis and static timing analysis
* Hands-on experience with Design/Verification CAD tools such as ncsim, Design Compiler, Formality/Conformal, PrimeTime, etc. are highly desirable
* Experience or knowledge of system architecture, CPU & IP Integration, and power and clock management designs is highly desirable
* Familiarity with Linux operating concepts
* Familiarity with scripting languages like Perl, Python, and Tcl is a plus
* Good oral and written communication skills - ability to effectively convey technical concepts
* Good people and collaborative skills - ability to work with cross-functional teams to meet goals
* Self-motivated and has the initiative to get things done on time and with high quality
* Ability to establish and maintain aggressive schedules for owned design responsibilities

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