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Sr Fpga Design Engineer
confidential | Irvine, California
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Job Description

Sr. FPGA Design Engineer sought by Netlist, Inc. in Irvine, CA: perform RTL (register-transfer level) dsgn, verification, validation of FPGA. Resume to: Janet Carter/Netlist, 175 Technology, Ste 150, Irvine, CA 92618. REF. JOB CODE: JS-01
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About confidential

Our client is a progressive-minded, rapidly growing consultancy in Phoenix with clients across the country. They provide outsourced and advisory services to some of the top nation-wide financial institutions. Our client is passionate about providing world-class opportunity for growth to their top performers, and is scaling their business with this strategy at the forefront.