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Intern - WFO
(This job is no longer available)
Cadence Design Systems | Austin, TX
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Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

What opportunity is offered?

Candidates will find an opportunity in the Digital Synthesis, Place and Route and Signoff Analysis Application Engineering group.

As an intern, you will gain exposure with high-performance and low-power block implementation and signoff flows from RTL to GDSII. The intern will have the opportunity to participate in a three month program consisting of training and application of engineering software solutions for physical synthesis of Verilog, place and route flows and signoff timing analysis. The intern will also have an opportunity to interact and learn from Senior Application Engineers in pre-sale and post-sale roles.

How long is this Internship?

Duration of this Internship is three [3] months.

What benefits do Interns receive?

* Competitive pay and eligibility to participate in 401k benefits
* Working for one of the Fortune 100 Best Companies to work for
* Real world work experience and exposure to EDA technology
* Opportunity to work with engineering and business experts
* Opportunity to network and participate in fun activities with the intern and recent college grad community at Cadence

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About Cadence Design Systems

Cadence Design Systems, Inc. (Cadence) develops electronic design automation (EDA) software and hardware. It licenses software, sells or leases hardware technology and provides engineering and education services worldwide to help manage and accelerate electronics product development processes. The Company offers three license types for its software: perpetual, term and subscription. The Company combines its products and technologies into platforms for four design activities: functional verification, digital integrated circuit (IC) design and implementation, custom IC design and verification, and system interconnect design. These are branded as Incisive functional verification, Encounter digital IC design, Virtuoso custom design, and Allegro system interconnect design. (Source: 10-K)