Experience:
Not specified
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Employment Type:
Full time
Posted:
9/16/2018
Job Category:
Engineering
Engineer
(This job is no longer available)
Apple Inc | Cupertino, CA
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Job Description

TECHNOLOGY Apple Inc. has multiple positions available in Cupertino, CA: Network Engineer (Req#9WXRWM) Dsgn, implmnt & supp high prfrmnce datacenter ntwrks. Hardware Development Engineer (Req#ARV4SB) Dsgn & dev HW for iMac comps. Travel req. 15%. Senior Finance Project Coordinator (Req#AZJFQT) Dvlp, implmnt, & maintain in-house & 3rd party developed financial sys. Software Development Engineer (Req#9WXRGK) Devlop Graphcal User Intrface (GUI) & Commnd-Line tools to visualze complx real-tme data sets. Hardware Development Engineer (Req#A9MVWE) Devlop SW to automte engnring data collction. Product Design Engineer (Req#A6C9CT) Dvlp, tst, & implment tech for future Apple products. Travel req. 25%. Senior Graphics Engineer, Platform Architecture (Req#9TTU3V) Crt wklds to vsually shwcse the ablties of mobl pltfrms. Software Engineer Applications (Req#ASJ4YL) Dsgn, dvlp, & deploy sftwre apps fr data-warehous & busines intel prjcts in Appl GBI compliance dept. CAD Engineer (Req#AUA387) Custmize App Lifecycl Mgmt (ALM) tools & dvlp intrfces to othr Aple's intrnal tools thrgh App Prgrm Intrfce (API) & Open Servces for Lifecycl Collab (OSLC). ASIC Design Engineer (Req#AKKUWQ) Resp for synthesizing blocks & full-chip using leading industry standard tools. Hardware Development Engineer (Req#ALDVKL) Collab w/ HW & SW dsgn teams to ensure test procedures used on new prducts meet standard req. in high volume. Travel req. 15%. ASIC Design Engineer (Req#ADDLKN) Dsgn and dvlp DFT (Dsgn-for-Test) archtctr and implmntaton for intgrtd crcit. Software Development Manager (Req#9GA2SH) Des & lead devlmnt of Siri SW & languages. ASIC Design Engineer (Req#AQFVJM) Crte sw to vrify archt. & fnctinlty of pre-slicn hw dsgns. ASIC Design Engineer (Req#ANB4SS) Work on PHY dsgn by interfacing w/ archtre, CAD, timing & logic dsgn teams. ASIC Design Engineer (Req#AP74HV) Crte sw to vrify archt. & fnctinlty of pre-slicn hw dsgns. ASIC Design Engineer (Req#AEPTJR) Crte sw to vrify archt. & fnctinlty of pre-slicn hw dsgns. ASIC Design Engineer (Req#ARK37M) Wrk clsely wth th Desgn & Micro Archtctre teams to undrstnd th fnctionl & prfrmnce goals of th design. ASIC Design Engineer (Req#ADEGRP01) Crte sw to vrify archt. & fnctinlty of pre-slicn hw dsgns. ASIC Design Engineer (Req#AXQV2D) Perf trnsistr-lvl feasibility stdy for anlog & mxd-sgnl crcuit blcks. ASIC Design Engineer (Req#AXQV3P) Pln & dsgn Systmverilg based tstbnches for vrfyng SOCs to be used on Apl's mobile devces. ASIC Design Engineer (Req#ALZ4FR) Supp FPGA-based prototyping sys for SW bringup & verification/validation tasks. Software Engineer Applications (Req#AQERTH) Rspnsble for the devpmnt, dsgn & debugng of SW for iOS rtail systms. Software Quality Assurance Engineer (Req#AN32GE) Tst sftwre usng indstry stndrd & inhouse tools. Refer to Req# & mail resume to Apple Inc., ATTN: D.W., 1 Infinite Loop 104-1GM, Cupertino, CA 95014. Apple is an EOE/AA m/f/disability/vets. Apple Inc. has multiple positions available in Cupertino, CA: Hardware Development Engineer (Req#9UPVP9) Desgn, spcify & prform qualifction of dsplay cmponnts used in Apple prodcts. Travel req. 20%. ASIC Design Engineer (Req#AJB7T6) Crte sw to vrify archt. & fnctinlty of pre-slicn hw dsgns. Technical Business Systems Analyst (Req#A4Z8XX) Defne prodct strtegy & roadmp for globl paymnts prtfolio. Travel req. 15% Machine Learning Engineer (Req#AEMTK3) Dsgn & dev HW architctre for comp vision & mchne learng apps. ASIC Design Engineer (Req#AKESJC) Collab w/ architecture team to define, anlyze, & document micro-architecture specs of the HW dsgn blocks. Refer to Req# & mail resume & transcript(s) to Apple Inc., ATTN: D.W., 1 Infinite Loop 104-1GM, Cupertino, CA 95014. Apple is an EOE/AA m/f/disability/vets.
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