Implement all circuits from RTL Verilog to layout.
Transistor-level circuit design of very high speed embedded SRAM macros.
Circuit simulation, layout extraction, timing characterization, and timing model generation.
Layout floor-planning and layout supervision.
Circuit-level logical functional verification.
Minimum GPA: 3.5
BSEE; MSEE or PhD preferred.
Prior internship experience with strong background in dynamic circuit design.
Prior design experience in single-port, dual-port, multi-port, or register file SRAM-based macros required.
Successful track record of delivering products to production is a must.
Self-motivated, good communication and teamwork skills are a must.
About NVIDIA Corporation
NVIDIA is the world leader in visual computing technologies and the inventor of the GPU, a high-performance processor which generates breathtaking, interactive graphics on workstations, personal computers, game consoles, and mobile devices. NVIDIA serves the entertainment and consumer market with its GeForce® products, the professional design and visualization market with its Quadro® products, and the high-performance computing market with its Tesla™ products. NVIDIA is headquartered in Santa Clara, Calif. and has offices throughout Asia, Europe, and the Americas. For more information, visit www.nvidia.com.